This invention is applicable to a multiprocessor system using a shared memory controller supporting access to memories that are arranged in banks which can be individually powered down. The shared memory controller supports consecutive speculative prefetch accesses to the memories based on the last access made by a CPU. The shared memory controller stores prefetched data in buffers. A read access to data already stored in a prefetch buffer reduces latency on such subsequent accesses. It is possible for the speculative prefetch accesses to cross memory bank boundaries from a memory bank that is powered up to one that is powered down.
Accessing a powered down memory row may result in corrupt data being stored in the prefetch buffer. This potentially corrupts data in memory as well. To prevent this from happening, the powered down memory must be woken up before the prefetch request is dispatched. The prefetch requests are only speculative access and have a low priority resulting in a long latency. Generally the software is written so that a prefetch is confined to powered memory banks. Thus the overhead incurred in waking up the memory is unnecessary and may result in additional power consumption, since the unused row may remain powered up.